Routing for analog chip designs at NXP Semiconductors

J.M. van den Akker, T. Beelen, R.H. Bisseling, B.O. Fagginger Auer, F. von Heymann, T. Müller, J. Rommes

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademic

Abstract

During the study week 2011 we worked on the question of how to automate certain aspects of the design of analog chips. Here we focused on the task of connecting different blocks with electrical wiring, which is particularly tedious to do by hand. For digital chips there is a wealth of research available for this, as in this situation the amount of blocks makes it hopeless to do the design by hand. Hence, we set our task to finding solutions that are based on the previous research, as well as being tailored to the specific setting given by NXP. This resulted in an heuristic approach, which we presented at the end of the week in the form of a protoype tool. In this report we give a detailed account of the ideas we used, and describe possibilities to extend the approach.
Original languageEnglish
Title of host publicationProceedings of the 79th European Study Group Mathematics with Industry
EditorsBob Planqué, Sandjai Bhulai, Joost Hulshof, Wouter Kager, Thomas Rot
PublisherVU University Amsterdam
Pages117-131
Number of pages15
Publication statusPublished - 24 Jan 2011

Keywords

  • Wiskunde en Informatica (WIIN)
  • Mathematics
  • Wiskunde en computerwetenschappen
  • Landbouwwetenschappen
  • Wiskunde: algemeen

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