Routing for analog chip designs at NXP Semiconductors

J.M. van den Akker; T. Beelen; R.H. Bisseling; B.O. Fagginger Auer; F. von Heymann; T. Müller; J. Rommes

Routing for analog chip designs at NXP Semiconductors

J.M. van den Akker, T. Beelen, R.H. Bisseling, B.O. Fagginger Auer, F. von Heymann, T. Müller, J. Rommes

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Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic

Abstract

During the study week 2011 we worked on the question of how to automate certain aspects of the design of analog chips. Here we focused on the task of connecting different blocks with electrical wiring, which is particularly tedious to do by hand. For digital chips there is a wealth of research available for this, as in this situation the amount of blocks makes it hopeless to do the design by hand. Hence, we set our task to finding solutions that are based on the previous research, as well as being tailored to the specific setting given by NXP. This resulted in an heuristic approach, which we presented at the end of the week in the form of a protoype tool. In this report we give a detailed account of the ideas we used, and describe possibilities to extend the approach.

Original language	English
Title of host publication	Proceedings of the 79th European Study Group Mathematics with Industry
Editors	Bob Planqué, Sandjai Bhulai, Joost Hulshof, Wouter Kager, Thomas Rot
Publisher	VU University Amsterdam
Pages	117-131
Number of pages	15
Publication status	Published - 24 Jan 2011

Keywords

Wiskunde en Informatica (WIIN)
Mathematics
Wiskunde en computerwetenschappen
Landbouwwetenschappen
Wiskunde: algemeen

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title = "Routing for analog chip designs at NXP Semiconductors",

abstract = "During the study week 2011 we worked on the question of how to automate certain aspects of the design of analog chips. Here we focused on the task of connecting different blocks with electrical wiring, which is particularly tedious to do by hand. For digital chips there is a wealth of research available for this, as in this situation the amount of blocks makes it hopeless to do the design by hand. Hence, we set our task to finding solutions that are based on the previous research, as well as being tailored to the specific setting given by NXP. This resulted in an heuristic approach, which we presented at the end of the week in the form of a protoype tool. In this report we give a detailed account of the ideas we used, and describe possibilities to extend the approach.",

keywords = "Wiskunde en Informatica (WIIN), Mathematics, Wiskunde en computerwetenschappen, Landbouwwetenschappen, Wiskunde: algemeen",

author = "{van den Akker}, J.M. and T. Beelen and R.H. Bisseling and {Fagginger Auer}, B.O. and {von Heymann}, F. and T. M{\"u}ller and J. Rommes",

year = "2011",

month = jan,

day = "24",

language = "English",

pages = "117--131",

editor = "Bob Planqu{\'e} and Sandjai Bhulai and Joost Hulshof and Wouter Kager and Thomas Rot",

booktitle = "Proceedings of the 79th European Study Group Mathematics with Industry",

publisher = "VU University Amsterdam",

}

Routing for analog chip designs at NXP Semiconductors. / van den Akker, J.M.; Beelen, T.; Bisseling, R.H. et al.
Proceedings of the 79th European Study Group Mathematics with Industry. ed. / Bob Planqué; Sandjai Bhulai; Joost Hulshof; Wouter Kager; Thomas Rot. VU University Amsterdam, 2011. p. 117-131.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic

TY - GEN

T1 - Routing for analog chip designs at NXP Semiconductors

AU - van den Akker, J.M.

AU - Beelen, T.

AU - Bisseling, R.H.

AU - Fagginger Auer, B.O.

AU - von Heymann, F.

AU - Müller, T.

AU - Rommes, J.

PY - 2011/1/24

Y1 - 2011/1/24

N2 - During the study week 2011 we worked on the question of how to automate certain aspects of the design of analog chips. Here we focused on the task of connecting different blocks with electrical wiring, which is particularly tedious to do by hand. For digital chips there is a wealth of research available for this, as in this situation the amount of blocks makes it hopeless to do the design by hand. Hence, we set our task to finding solutions that are based on the previous research, as well as being tailored to the specific setting given by NXP. This resulted in an heuristic approach, which we presented at the end of the week in the form of a protoype tool. In this report we give a detailed account of the ideas we used, and describe possibilities to extend the approach.

AB - During the study week 2011 we worked on the question of how to automate certain aspects of the design of analog chips. Here we focused on the task of connecting different blocks with electrical wiring, which is particularly tedious to do by hand. For digital chips there is a wealth of research available for this, as in this situation the amount of blocks makes it hopeless to do the design by hand. Hence, we set our task to finding solutions that are based on the previous research, as well as being tailored to the specific setting given by NXP. This resulted in an heuristic approach, which we presented at the end of the week in the form of a protoype tool. In this report we give a detailed account of the ideas we used, and describe possibilities to extend the approach.

KW - Wiskunde en Informatica (WIIN)

KW - Mathematics

KW - Wiskunde en computerwetenschappen

KW - Landbouwwetenschappen

KW - Wiskunde: algemeen

M3 - Conference contribution

SP - 117

EP - 131

BT - Proceedings of the 79th European Study Group Mathematics with Industry

A2 - Planqué, Bob

A2 - Bhulai, Sandjai

A2 - Hulshof, Joost

A2 - Kager, Wouter

A2 - Rot, Thomas

PB - VU University Amsterdam

ER -

Routing for analog chip designs at NXP Semiconductors

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