Pushing the limit of lithography for patterning two-dimensional lattices in III-V semiconductor quantum wells

N. A.Franchina Vergel; C. Post; F. Vaurette; Y. Lambert; D. Yarekha; C. Coinon; G. Fleury; T. S. Kulmala; T. Xu; L. Desplanque; X. Wallart; D. Vanmaekelbergh; C. Delerue; B. Grandidier

doi:10.1109/EDTM50988.2021.9420884

Pushing the limit of lithography for patterning two-dimensional lattices in III-V semiconductor quantum wells

N. A.Franchina Vergel, C. Post, F. Vaurette, Y. Lambert, D. Yarekha, C. Coinon, G. Fleury, T. S. Kulmala, T. Xu, L. Desplanque, X. Wallart, D. Vanmaekelbergh, C. Delerue, B. Grandidier

Shanghai University

Research output: Chapter in Book/Report/Conference proceeding › Chapter › Academic › peer-review

Abstract

Building two-dimensional lattices in semiconductor quantum-wells offers the prospect to design distinct energy-momentum dispersions, including conical intersections and nondispersive bands. Here, we compare three lithographic patterning methods, e-beam lithography, block copolymer lithography and thermal scanning probe lithography to produce a honeycomb lattice in an In0.53Ga0.47As quantum well. We weigh up the pros and cons of each method to reach lattice constants smaller than 20 nm with a minimum of dispersion in the pore size.

Original language	English
Title of host publication	2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)
Publisher	IEEE
Pages	1-3
Number of pages	3
ISBN (Print)	9781728181769
DOIs	https://doi.org/10.1109/EDTM50988.2021.9420884
Publication status	Published - 8 Apr 2021

Keywords

III-V semiconductors
Lithography
two-dimensional lattices

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10.1109/EDTM50988.2021.9420884

Pushing_the_limit_of_lithography_for_patterning_two-dimensional_lattices_in_III-V_semiconductor_quantum_wellsFinal published version, 779 KBLicence: Taverne

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Vergel, N. A. F., Post, C., Vaurette, F., Lambert, Y., Yarekha, D., Coinon, C., Fleury, G., Kulmala, T. S., Xu, T., Desplanque, L., Wallart, X., Vanmaekelbergh, D., Delerue, C., & Grandidier, B. (2021). Pushing the limit of lithography for patterning two-dimensional lattices in III-V semiconductor quantum wells. In 2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM) (pp. 1-3). IEEE. https://doi.org/10.1109/EDTM50988.2021.9420884

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abstract = "Building two-dimensional lattices in semiconductor quantum-wells offers the prospect to design distinct energy-momentum dispersions, including conical intersections and nondispersive bands. Here, we compare three lithographic patterning methods, e-beam lithography, block copolymer lithography and thermal scanning probe lithography to produce a honeycomb lattice in an In0.53Ga0.47As quantum well. We weigh up the pros and cons of each method to reach lattice constants smaller than 20 nm with a minimum of dispersion in the pore size.",

keywords = "III-V semiconductors, Lithography, two-dimensional lattices",

author = "Vergel, {N. A.Franchina} and C. Post and F. Vaurette and Y. Lambert and D. Yarekha and C. Coinon and G. Fleury and Kulmala, {T. S.} and T. Xu and L. Desplanque and X. Wallart and D. Vanmaekelbergh and C. Delerue and B. Grandidier",

year = "2021",

month = apr,

day = "8",

doi = "10.1109/EDTM50988.2021.9420884",

language = "English",

isbn = "9781728181769",

pages = "1--3",

booktitle = "2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)",

publisher = "IEEE",

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Vergel, NAF, Post, C, Vaurette, F, Lambert, Y, Yarekha, D, Coinon, C, Fleury, G, Kulmala, TS, Xu, T, Desplanque, L, Wallart, X, Vanmaekelbergh, D, Delerue, C & Grandidier, B 2021, Pushing the limit of lithography for patterning two-dimensional lattices in III-V semiconductor quantum wells. in 2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM). IEEE, pp. 1-3. https://doi.org/10.1109/EDTM50988.2021.9420884

TY - CHAP

T1 - Pushing the limit of lithography for patterning two-dimensional lattices in III-V semiconductor quantum wells

AU - Vergel, N. A.Franchina

AU - Post, C.

AU - Vaurette, F.

AU - Lambert, Y.

AU - Yarekha, D.

AU - Coinon, C.

AU - Fleury, G.

AU - Kulmala, T. S.

AU - Xu, T.

AU - Desplanque, L.

AU - Wallart, X.

AU - Vanmaekelbergh, D.

AU - Delerue, C.

AU - Grandidier, B.

PY - 2021/4/8

Y1 - 2021/4/8

N2 - Building two-dimensional lattices in semiconductor quantum-wells offers the prospect to design distinct energy-momentum dispersions, including conical intersections and nondispersive bands. Here, we compare three lithographic patterning methods, e-beam lithography, block copolymer lithography and thermal scanning probe lithography to produce a honeycomb lattice in an In0.53Ga0.47As quantum well. We weigh up the pros and cons of each method to reach lattice constants smaller than 20 nm with a minimum of dispersion in the pore size.

AB - Building two-dimensional lattices in semiconductor quantum-wells offers the prospect to design distinct energy-momentum dispersions, including conical intersections and nondispersive bands. Here, we compare three lithographic patterning methods, e-beam lithography, block copolymer lithography and thermal scanning probe lithography to produce a honeycomb lattice in an In0.53Ga0.47As quantum well. We weigh up the pros and cons of each method to reach lattice constants smaller than 20 nm with a minimum of dispersion in the pore size.

KW - III-V semiconductors

KW - Lithography

KW - two-dimensional lattices

UR - https://www.mendeley.com/catalogue/ddae0293-4934-33a2-a7a2-66ea0530e014/

U2 - 10.1109/EDTM50988.2021.9420884

DO - 10.1109/EDTM50988.2021.9420884

M3 - Chapter

SN - 9781728181769

SP - 1

EP - 3

BT - 2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)

PB - IEEE

ER -

Pushing the limit of lithography for patterning two-dimensional lattices in III-V semiconductor quantum wells

Abstract

Keywords

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